Vertical field-effect semiconductor device with buried gate region

ABSTRACT

A buried gate region, a buried gate contact region and a gate contact region are provided on an SiC substrate. Thereby, a depletion layer expands in the channel region, and a high withstand voltage is attained in the normally off state. By applying a voltage of the built-in voltage or less to a gate, the depletion layer in the channel region becomes narrower and an ON-state resistance becomes low. Furthermore, when a voltage of the built-in voltage or more is applied to the gate, holes are injected from the gate so as to cause the conductivity modulation, and the ON-state resistance becomes further low.

TECHNICAL FIELD

The present invention relates to an improvement of a field effectsemiconductor device.

BACKGROUND ART

As a vertical type power semiconductor device having a small input loss,being excellent in high speed switching characteristics, and having ahigh input impedance, for example, a Metal Oxide Semiconductor FieldEffect Transistor (MOSFET) is known. FIG. 8 is a cross-sectional view ofa trench gate type MOSFET of a prior art. In this trench gate typeMOSFET of the prior art, by employing a trench type structure forming agate 106 in a recess 110, an efficient utilization of the surface areais intended; and it is intended to reduce power loss. Recently, a powersemiconductor device using a single crystal material of silicon carbide(SiC) has been produced by way of trial; and as for the trench gate typeMOSFET of FIG. 8, an n-type drift layer 102 is formed on a semiconductorsubstrate 101 of an n-type silicon carbide by epitaxial method. A p-typebody layer 103 is formed on the n-type drift layer 102, and in addition,an n-type source region 104 is formed in a predetermined region of thep-type body layer. The recesses 110 are formed at both the end parts ofthe n-type source region 104 and the p-type body layer 103 so as toreach the n-type drift layer 102, and gate electrodes 106 are formed viarespective gate insulating films 105 formed on the surface of therecesses 110. A source electrode 108 is formed on the p-type body layer103 and the n-type source regions 104. A drain electrode 107 is formedon the bottom surface of the n-type silicon carbide semiconductorsubstrate 101.

A voltage is applied to the gate electrode 1061 and an electric field isgiven to the gate insulating films 105 of the recess parts placedbetween the gate electrodes 106 and the p-type body layer 103 of therecess sidewall part, and thereby, the conductive type of the p-typebody layer 103 which contacts the gate insulating film 105 is invertedto the n-type so as to form a channel which makes the carriers flowbetween the source S and the drain D.

FIG. 9 is a cross-sectional view of an ACCUFET (accumulation fieldeffect transistor: see IEEE Electron Device Letters, vol. 18, No. 12,December 1997) which uses SiC according to another prior art. In theACCUFET, a p+-type buried region 109 is formed by injecting ions into adrift layer 102. This buried region 109 is connected to a source region104 with a connection wire 115 so as to be at the same potential as thesource region 104, and thereby, an electric field at the lower part ofthe gate insulating film 105 is alleviated. By making the buried region109 and the source region 104 identical in potential, a depletion layerexpands in a channel part 111 due, to the existence of a built-involtage of the junction, and without applying a gate voltage to the gateG, a normally off operation becomes possible, so as to interrupt acurrent between the drain,D and the source S, and in addition, itbecomes advantageous to heighten a withstand voltage.

In the vertical type semiconductor device which has the trench structureof the trench gate type MOSFET, or the like, in FIG. 8, when it isintended to heighten a withstand voltage, electric field tends toconcentrate at the bottom parts or at the corner parts of the trench110, therefore, it is difficult to heighten the withstand voltage.Particularly in a semiconductor device using SiC, since the insulationbreakcdown electric field is high, the impurity density of the driftlayer 102 can be made high so as to lower the resistance thereof. As aresult, the electric field in the vicinity of the gate insulating film105 at the bottom part of the trench 110 becomes higher and it isdifficult to heighten the withstand voltage. In addition, though it isnecessary to make the gate voltage high in order to implement a lowON-state resistance, when a high gate voltage is applied, the electricfield in the vicinity of the gate insulating film 105 becomes high so asto lower the reliability of the device.

Moreover, in the vertical type semiconductor device which has the trenchstructure, because of the influence of the process for forming thetrench 110, the interface state density which exists at the interfacebetween the gate insulating film 105 and the drift layer 102 becomeslarge and the roughness of the interface becomes greater. Because ofthat influence, the mobility of the channel which is a current path inON-state becomes small and, as a result, an ON-state resistance becomeslarge.

In an ACCUFET semiconductor device or the like, which does not have thetrench structure of FIG. 9, since no trenches are formed, the interfacestate density is not large and, the influence of the roughness of theinterface is small unlike in a semiconductor device of a trenchstructure. In addition, in the case that a high voltage is applied tothe drain D at OFF-state, a depletion layer expands from the p+-buriedregion 109 to the side of the drain electrode 107, bringing the areabetween the buried region 109 and the drift layer into a pinch off statethereby to withstand a high voltage, and therefore, a high electricfield is not applied to the gate insulating film 105. In order tomaintain the normally OFF-state, that is to say, the OFF-state even whenthe drain voltage is 0 V in this structure, however, it is necessary tobring the channel region 111 into a pinch off state by means of adepletion layer formed by the built-in voltage in the junction partbetween the buried region 109 and the channel 111 located above.Therefore, the channel width of the channel region 111 has to be narrow.On the other hand, in order to realize a low ON-state resistance at theON-state, the width of the channel needs to be made wider, andtherefore, it is difficult to realize both the maintenance of thenormally OFF-state and the low ON-state resistance at the ON-state.

DISCLOSURE OF THE INVENTION

The present invention purposes to provide a semiconductor device whichalleviates the electric field at the lower parts of the gate insulatingfilm 105, being low in an ON-state resistance, high in a withstandvoltage and high in reliability.

In a semiconductor device of the present invention, a channel region ofthe first conductive type of a low impurity density comprising a sourceregion of the first conductive type of a high impurity density is formedso as to contact, except for a portion of the bottom part thereof, aburied gate region, a buried gate contact region and a surface gatecontact region of the second conductive type. In addition, it has theconfiguration wherein a gate electrode is provided so as to face saidchannel region between the source region of the first conductive typeand the surface gate contact region of the second conductive type via aninsulating film.

According to the configuration-, when a voltage equal to or below thebuilt-in voltage of the junction is applied to the gate electrode at theON-state, the depletion layer expanding into the above-mentioned channelregion contracts into a narrow range of the channel region. Therefore,the channel width through which a current flows becomes wide so that alow ON-state resistance is realizable at a low gate voltage.

At the OFF-state, a depletion layer expands from the junction of theburied gate region as well as the buried gate contact region of thesecond conductive type and the drift layer, to the side of the drain soas to pinch off the area between both of the buried regions and supporta voltage and, therefore, a high electric field is not applied to thegate insulating film and a semiconductor device of a high reliability isobtainable.

In addition, in an area between the buried gate region of the secondconductive type and the buried gate contact region of the secondconductive type, in order to maintain the ON-state resistance at a lowvalue and to reduce the gate resistance, buried gate connection regionsof the second conductive type are formed being spaced with predeterminedintervals from each other. Thereby, the three regions of the secondconductive type are electrically connected.

By this structure, the depletion layer expanding through the channelregion can be made to contract to a narrow range, not only in the upwardand downward directions but also in all directions, by applying avoltage equal to the built-in voltage and below to the gate. As aresult, the channel width can be wide, and a low ON-state resistance isrealizable even in a low gate voltage. In addition, the normally offcondition can be easily implemented and a higher withstand voltage canbe achieved.

In particular, since the gate is divided into a MOS insulated gate and aburied gate, respective gates can be controlled independently. When avoltage that is higher than that to the buried gate is applied to theMOS insulated gate, a further large storage effect of carriers can beattained so that the ON-state resistance can be further lowered.

In addition, by applying a voltage equal to the built-in voltage orhigher to the gate, holes are injected to the channel region from theburied gate of the second conductive type so as to conductivity-modulatelayer of the first conductive type, and the ON-state resistance can befurther reduced.

In particular, the buried gate region of the second conductive type isformed through ion implantation of impurities having a low activationratio, and the buried gate contact region of the second conductive typeis formed by an ion implantation of impurities having a high activationratio. Thereby, holes are injected from the buried gate contact regionof the second conductive type, so that the conductivity modulationoccurs effectively, and the ON-state resistance can be further lowered.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a field effect transistor accordingto a first embodiment of the present invention;

FIG. 2(a) is a cross-sectional view showing a buried gate region of afield effect transistor according to a'second embodiment of the presentinvention;.

FIG. 2(b) is a cross-sectional view taken along line b—b of FIG. 2(a);

FIG. 3 is a cross-sectional view of a field effect transistor accordingto a third embodiment of the present invention;

FIG. 4 is a cross-sectional view of a field effect transistor accordingto a fourth embodiment of the present invention;

FIG. 5 is a cross-sectional view of a field effect transistor accordingto a fifth embodiment of the present invention;

FIG. 6 is a cross-sectional view of a thyristor according to a sixthembodiment of the present invention;.

FIG. 7 is a cross-sectional view of a GTO according to a seventhembodiment of the present invention;

FIG. 8 is the cross-sectional view of the trench type field effectsemiconductor device according to the prior art; and

FIG. 9 is the cross-sectional view of the plane type field effectsemiconductor device according to the prior art.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereafter, preferred embodiments of the present invention are describedwith reference to FIG. 1 to FIG. 7. FIG. 1 to FIG. 7 respectively showone segment of a semiconductor device of each embodiment, and a numberof these segments are connected in the right and left directions of thefigure so as to form a semiconductor device of a large capacity. In eachfigure, the dimensions of each of the illustrated elements do notcorrespond to the actual dimensions.

FIRST EMBODIMENT

FIG. 1 is a cross-sectional view of a segment of an SiC (siliconcarbide) field effect transistor of 5 kV of withstand voltage accordingto the first embodiment of the present invention, and the segment has astripe shape which is long in the direction vertical to the paper face.In FIG. 1, an n-type SiC drift layer 2 of a low impurity density of thethickness of approximately 60 μm is formed on an n-type SiC drain region1 of a high impurity density of the thickness approximately 300 μm. Ann-type SiC source region 4 which is-connected to the source electrode 12is 0.2 μm in thickness, which may be approximately 0.1 μm to 0.3 μm. Thethickness of the gate insulating film 8 is 0.10 μm. The optimal value ofthe thickness of the p+-type SiC buried gate region 5 is 0.3 μm.However, it may have the value of from 0.1 μm to 0.5 μm. The optimalthickness of an n-type channel region 3 is 0.3 μm. However, it may havethe value of from 0.1 μm to 0.5 μm. The width of the p+-type buried gateregion 5 is preferably longer than the n-type source region 4 byapproximately 5 μm. However, it may be longer by the value of from 3 μmto 10 μm. The gap between the p+-type buried gate region 5 and thep+-type buried gate contact region 6 is optimal at the value of 3 μm.However, it may have the value of from 2 μm to 5 μm. In the presentembodiment, the gate electrode 13 is in a stripe shape which is long inthe direction vertical to the paper face. However, the form may be, forexample, circular, rectangular, etc.

One example of a manufacturing process for the field effect transistorof the present embodiment is as follows. An n-type SiC substrate of ahigh impurity density of 10¹⁸ to 10²⁰atm/cm³which functions as the drainregion 1 is provided and, on one of the surfaces thereof, an n-type SiCdrift layer 2 of a low impurity density of 10¹⁴ to 10¹⁶ atm/cm³ isformed by a chemical vapor deposition method, or the like. Next, ap+-type buried gate region 5 of approximately 10¹⁸ atm/cm³ and a p+-typeburied gate contact region 6 are formed by through an-ion implantationof aluminum, or the like, and, on top thereof, a channel region 3 of ann-type SiC drift layer of a low impurity density of 10¹⁴ to 10¹⁶ atm/cm³is formed again thereon by a chemical vapor deposition method, or thelike. Subsequently, at both end parts of the channel region 3, a p+-typegate contact region 7 which reaches to the p+-type buried gate contactregion 6 is formed by an ion implantation method of aluminum, or thelike.

Next, an n-type source region 4 of a high impurity density of 10¹⁸ to10²⁰ atm/cm³ is formed in the central part of the channel region 3 by anion implantation method of nitrogen, or the like. After forming aninsulating film 8 of SiO2 on the channel region 3, the n-type sourceregion 4 and the p-type gate contact region 7, the SiO2 insulating film8 is removed from both end parts of the p+-type gate contact region 7,and a gate electrode 13 which is connected to the p-type gate contactregion 7 is formed by a metal film of Al, or the like. In addition, theSiO2 insulating film 8 on the central part of the n-type source region 4is removed and a source electrode 12, which is connected to the n-typesource region 4, is formed by a metal film such as aluminum or nickel.Furthermore, a portion of the buried gate region 5 is exposed at oneposition in the depth direction (in the direction vertical to thepaperface of FIG. 1) of the segment, and an electrode G1 is connected tothe exposed buried gate region 5 so as to be lead out to the side of thesource electrode 12. Finally, a drain electrode 11, which is connectedto the drain region 1, is formed by aluminum, nickel, or the like, andthereby resulting in completion.

In the SiC field effect transistor of the present embodiment, when thepotentials between the gates G1, G2 and the source S is set to 0 V underthe condition that the potential of the drain D is higher than thepotential of the source S, a depletion layer corresponding to thebuilt-in voltage expands from the junction part between the buried gateregion 5 and the n-type drift layer 2 as well as the n-type channelregion 3 which contact the buried gate region 5, and the channel region3 can be made to a pinch off state. As a result, a current between thesource S and the drain D can be cut off, and thereby resulting in anormally OFF-state. At this time, a depletion layer expands from thejunction between the p+-type buried gate region 5 as well as the buriedgate contact region 6 and the n-type drift layer 2 on the side of thedrain D so as to bring the channel region 3 between the buried gateregion 5 and the buried gate contact region 6 into the pinch off state.The depletion layer also expands to the side of the drain D, and sincethe depletion layer of this n-type drift layer 2 supports the voltage, ahigh electric field can be prevented from application to the gateinsulating film 8, and thus a high reliability, is attainable. Inaddition, by applying a negative voltage to the gate G1, the channelregion 3 can be in the pinch off state with a high drain voltage so thata withstand voltage can be heightened.

When a gate voltage is applied so that the potential of the drain D ishigher than the potential of the source S and the potentials-of thegates G1, G2 are higher than the potential of the source S, thedepletion layers in the channel region 3 and between the p+-type buriedgate region 5 and the p+-type buried gate contact region 6 become narrowand the ON-state resistance reduces. The gate electrode 13 and thechannel region 3 which faces the electrode 13 via the insulating film 8form a MOS field effect element. Accordingly, in the above-mentionedvoltage applied condition, the channel resistance of the channel region3 is reduced owing to the storage effect of the carriers based on thefield effect of the MOS, and the ON-state resistance is further reduced.When the gate voltage is further increased, the depletion layer becomesnarrower and an increased number of electrons are stored in the channelregion 3, and thereby the ON-state resistance is further reduced.

The withstand voltage of the field effect transistor of this embodimentis -approximately, 5.3 kV when the gates G1, G2 are set to 0 V, and theON-state resistance is approximately 69 mΩcm² when the gate voltage is2.5 V which is higher than the threshold voltage at which the MOSstorage effect occurs. By applying −20 V to the gate. G1, the withstandvoltage can be increased to 6 kV. In addition, by bringing the gatevoltage into the built-in voltage (approximately 2.5 V for SiC) or less,only a current for the capacity of the depletion layer flows through thegates G1, G2, and the driving power can be suppressed to a low. Inaddition, in the case that the gate voltage is at the built-in voltageor more, holes are injected from the gates G1, G2, and therebyoccurrence of the conductivity modulation is made possible by theinjection of a small amount of holes. Thereby, a further low resistance,and therefore, a low ON-state voltage is realizable. In addition, thefield effect transistor of the present embodiment does not include atrench, and a reactive ion etching process is not carried out for atrench process. Accordingly, there is little negative influence causedby a surface state or by the roughness of the interface, which would bea problem in the trench part of a field effect transistor having atrench structure.

SECOND EMBODIMENT

FIG. 2(a) is a cross-sectional view of a field effect transistoraccording to the second embodiment of the present invention, and FIG.2(b) is a cross-sectional view taken along line b-b of FIG. 2(a)including a p+-type buried gate region 5 and a p+-type buried gatecontact region 6. In the field effect transistor according to the firstembodiment as shown in FIG. 1, the p+-type buried gate region 5 isconnected to the gate terminal G1 at a predetermined position in thedirection perpendicular to the paper face. Accordingly, at a positionspaced apart from the gate terminal G1 in the buried region 5 which islong in the direction perpendicular to the paper face, the resistance(gate resistance) between the gate terminal G1 and the buried gateregion 5 becomes high. The field effect transistor according to thesecond embodiment is provided with a plurality of p+-type buried gateconnection regions 9 at constant intervals between the p-type buriedgate region 5 and the p-type buried gate contact region 6 so as to makea connection therebetween. Except for this point, the structures of bothembodiments are almost the same. By providing a plurality of buried gateconnection regions 9, the p+-type buried gate region 5 and the p+-typeburied gate contact region 6 are electrically connected at a pluralityof positions. According to this configuration, the buried gate region 5is connected to the gate G2 via the buried gate contact regions 6 andthe p+-type gate contact regions 7 at constant intervals, and thereby,the gate resistance of the p-type buried gate region 5 can be greatlyreduced. For example, in the case .that p+-type buried gate connectionregions 9 are provided in an element of the length of 1 mm at intervalsof 100 μm, the gate resistance can be reduced to approximately one tenthwithout hardly increasing the ON-state resistance.

In addition, in this structure, by applying a voltage of the built-involtage or less of the p+ n-junction to the gate G2 so that thedepletion layer which expands to the channel region 3 is made narrowernot only in the upward and downward directions but also in the right andleft directions, the channel width can be made broader, so that a lowON-state resistance can be attained at a low gate voltage. A normallyOFF condition can also be easily realizable.

THIRD EMBODIMENT

FIG. 3 is a cross-sectional view of a segment of an SiC field effecttransistor according to the third embodiment of the present invention.In the present embodiment, an insulating film 17 is formed on the entiresurface of the gate electrode 13 and a source electrode 12A is formed onthe entire surface of the insulating film 17. The configuration is thesame as that of the first embodiment except for the point that theabove-mentioned source electrode 12A is provided on the gate electrode13 via the insulating film 17, and therefore, the overlappeddescriptions are omitted. In the configuration of FIG. 3, the area ofthe source electrode 12A becomes large so that the resistance thereofcan be greatly reduced. In the present embodiment, a source terminal Smay be connected to the source electrode 12A by wire bonding, or asource terminal plate 18 of a flat plate shape may be formed bypress-pack on the face of the source electrode 12A. In this manner, thestress caused by the pressure applied to the gate part including thegate electrode 13 is alleviated and a high reliability is attainable.

FOURTH EMBODIMENT

FIG. 4 is a cross-sectional view of a segment of an SiC field effecttransistor according to the fourth embodiment of the present invention.In the present embodiment, a gate electrode 13A is formed on a p-typegate contact region 7, and a MOS gate 13B of another gate electrode isformed on the gate insulating film 8. Other configurations are the sameas those in the first embodiment as shown in FIG. 1, and therefore, theoverlapped descriptions are omitted. By dividing the gate electrode intothe gate electrode 13A and the MOS gate 13B, gate voltages differentfrom each other can be applied to the gate electrode 13A and the MOSgate 13B; and thereby, the drift layer 2 adjacent to the buried gatecontact region 6 and the buried gate region 5, and the channel region 3which opposes to the MOS gate 13B via the insulating film 8 can beindependently controlled. Consequently, at the time of turning on, byapplying a voltage which is larger than that applied to the gateelectrode 13A connected to the buried gate contact region 6 to the MOSgate 13B, the storage effect of the carriers in the MOS structurebecomes larger so that the,ON-state resistance can be further reduced.For example, in a field effect transistor of 5.3 kV withstand voltage,when 5 V is applied to the MOS gate 13B and 2.5 V is applied to the gateelectrode 13A, the ON-state resistance becomes 54 m Ωcm² which isreduced by approximately 20% in comparison with the case where 2.5 V isapplied to the MOS gate 13B. When the voltage of the gate electrode 13Ais further raised, holes are injected to the channel region 3 from theburied gate region 5, the buried gate contact region 6 and the gatecontact region 7 so that the conductivity modulation occurs, and theON-state resistance further reduces, and can be made to 18 mΩcm². Inaddition, by applying a voltage of −20 V to the gate electrode 13A, thechannel region 3 can be pinched off even in the case that the drainvoltage is high, and thereby, the withstand voltage is heightened and ahigh withstand voltage of 6 kV has been realized.

FIFTH EMBODIMENT

FIG. 5 is a cross-sectional view of a segment of an SiC field effecttransistor according to the fifth embodiment of the present invention.In the present embodiment, steps are provided on both end parts of the 4segment of a field effect transistor so as to form a trench structure.Since the trench structure is employed, the channel region 3 results ina shape protruding from the n-type drift layer 2. A gate electrode 13Cis formed on the top face and the side face of the channel region 3 viaan insulating film 8A. Both end parts of the gate electrode 13C contactthe buried gate contact region 6. Other configurations are the same asthose of Embodiment 1 as shown in FIG. 1, and therefore, the overlappeddescriptions are omitted. When a positive voltage is applied to the gateelectrode 13C, the storage effect of the carries occurs on bothsidewalls of the channel region 3, and the region in which the carriersare stored can be made to extend to an area between the p-type buriedgate contact region 6 and the p-type buried gate region 5. Thereby, thefurther reduction of the On-state resistance can be intended. In thecase of a field effect transistor element of 5.3 kV of withstandvoltage, the ON-state resistance can be made to 61 mΩcm²

Incidentally, though both of the sidewalls are located between theburied gate region 5 and the buried gate contact region 6 in thisstructure, they may be located above the buried gate contact region 6.Thereby, the withstand voltage is slightly lowered, but the current pathbecomes wider so that the ON-state resistance can be further reduced.

SIXTH EMBODIMENT

FIG. 6 is a cross-sectional view of a segment of an SiC thyristoraccording to the sixth embodiment of the present invention. In thefigure, an n-type drift layer 2 of a low impurity density of 10¹⁴ to10¹⁶ atm/cm³ is formed by a chemical vapor deposition method or thelike, on a p-type SiC substrate,of a high impurity density of 10¹⁸ to10²⁰ atm/cm³ which functions as an anode region 21. In a manner similarto the case of the above-mentioned first embodiment, a p-type buriedgate region 5 and a p-type buried gate contact region 6 are formed onthe drift layer 2. In a similar manner, a p-type gate contact region 7,a channel region 3 and an n-type cathode region 22 are formed. A cathodeelectrode 15 is provided on the cathode region 22. A gate electrode 13is provided on the channel region 3 via the insulating film 8. The endpart of the gate electrode 13 contacts the gate contact region 7. Ananode electrode 14 is provided on the anode region 21.

When the gate G and the cathode K are set to 0 V and a positive voltageis applied to the anode A, a depletion layer based on the built-involtage expands in the junction part between the buried gate region 5and the channel region 3 so as to bring the channel region 3 into thepinch off state. Thereby, a withstand voltage characteristics arises towithstand a forward direction voltage. When the gate G and the cathode Kare set to 0 V and a negative voltage is applied to the anode A, adepletion layer expands to the junction part between the p+-type anoderegion 21 and the drift layer 2 so that the withstand voltagecharacteristics arises to withstand a reverse voltage. Therefore, a highwithstand voltage both in the forward direction and in the reversedirection is attainable in the SiC thyristor according to the presentembodiment. On the other hand, when a positive voltage is applied to theanode A, and a voltage of the built-in voltage or more with thereference to the cathode K is applied to the gate G, the thyristor partof the p+-type anode region 21, the n-type drift layer 2, the p+-typeburied gate region 5 and the n+-type cathode region turns ON. Sinceholes are-injected into the drift layer 2 from the anode region 21, theconductivity modulation arises so that the ON-state resistance greatlyreduces in the high current density region. In the case of a thyristorelement of 5.3 kV of withstanding voltage, the ON-state resistance afterthe current rise can be made to be 10 mΩcm²or less.

In the present embodiment, by limiting the impurity.density of thep+-type anode region 21 in a range of 10¹⁶ to 10¹⁸ atm/cm³, or byproviding an n-type high density region 2B between the p+-type anoderegion 21 and the n- drift region 2 as shown by a dotted line, theinjection amount of holes from the p+-type anode region 21 isrestricted, and thereby, the operation can be carried out as an IGBT.Though the ON-state resistance in this case is larger than the ON-stateresistance of the thyristor of 10 mΩcm² and becomes approximately 40mΩcm², there is an advantage that the switching speed is fast and thecurrent can be turned on or off only by turning on or off the gatesignal.

It is difficult to make the resistance low in the SiC p-type substrateof the initial material which becomes the anode region 21. Therefore, itis effective to make the p+-type anode region 21 thinner in order tofurther reduce the ON-state resistance (as described above, 10 mΩcm² inthe thyristor, and 40 mΩcm² in the IGBT) between the anode 21 and thecathode 15. Though in the above-mentioned case, the thickness isapproximately 80 to 200 μm, for example, by bringing the thickness intoapproximately 0.3 to 20 μm, the ON-state resistance of the thyristor orthe IGBT can be greatly reduced in a range of approximately {fraction(1/10)} (when it is 0.3 μm) to ½ (when it is 20 μm) without making theproduction excessively difficult. This case, for example, in theproduction method of embodiment 1, becomes possible by grinding orpolishing the p+-type anode region 21 to the above-mentioned thicknessbefore the drain electrode is formed. Furthermore, in the case that thep+-type anode region 21 is made to 1 μm or less, it is preferable toform a new p+-type region in the surface of the n-type drift region 2 bythe ion implantation of aluminum, boron or the like after the anoderegion 21 is completely removed by grinding or polishing.

SEVENTH EMBODIMENT

FIG. 7 is a cross-sectional view of a segment of a GTO thyristor (gateturn off thyristor) using SiC according to the seventh embodiment of thepresent invention. In the GTO thyristor using SiC of FIG. 7, n-type ischanged to p-type and p-type is changed to n-type in each component ofthe SiC thyristor of FIG. 6. In FIG. 7, a cathode electrode 15A isprovided on the cathode region 22A in the lower part, and an anodeelectrode 14A is provided on the anode region 21 in the upper part.

When the gate G and the anode A are set to 0 V and a negative voltage isapplied to the cathode K, a depletion layer based on the built-involtage expands in the vicinity of the junction part between the buriedgate region 5 and the channel region 3 thereon, and the channel region 3is made into a pinch off state. Thereby, the withstand voltagecharacteristic which withstands the forward direction voltage arises.When the gate G and the anode A are set to 0 V and a positive voltage isapplied to the cathode K, a depletion layer expands in the vicinity ofthe junction part between the cathode region 22A and the drift layer 2,and the withstanding voltage characteristic which withstands the reversedirection voltage arises. Accordingly, the GTO thyristor using SiC ofthe present embodiment is capable of realizing a high withstand voltageboth in the forward direction and in the reverse direction. On the otherhand, when a negative voltage is applied to the cathode K and a voltageof the built-in voltage or less is applied to the gate G with referenceto the anode A, the GTO thyristor turns ON. Since electrons are injectedinto the drift layer 2 from the cathode region 22, the conductivitymodulation occurs and the ON-state resistance of a high current densityregion is greatly reduced. In the state that the GTO thyristor is turnedon, by applying an inverse bias to the gate G and by extracting a partof the current flowing through the anode A and the cathode K from thegate G, the GTO thyristor can be made to OFF state.

EIGHTH EMBODIMENT

In the eighth embodiment of the present invention, with respect to thefield effect transistors of the above-mentioned first to fifthembodiments and the SiC thyristors of the sixth and seventh embodiments,the buried gate region 5 is formed by the ion implantation of boronhaving a low ion activation ratio, and the buried gate contact region 6is formed by the ion implantation of aluminum or the like having a highactivation ratio. Since the ion activation ratio of the buried gateregion 5 is low, almost no holes are injected from the buried gateregion 5, but rather, holes are injected from the buried gate contactregion 6 having the high activation ratio. Since these holes effectivelymodulate the conductivities of the channel region 3 and the drift layer2, the further reduction of the ON-state resistance can be attained. TheON-state resistance can be reduced by approximately 10% in comparisonwith those of the above-mentioned first to seventh embodiments.

Though, eight embodiments are described in the above, the presentinvention covers a wider scope of application and derivative structures.For example, the basic element may be an IGBT, or the like. The MOSgate, the buried gate region and the buried gate contact region may be,respectively separated so as to form a configuration of individual gatesas shown in the fourth embodiment, for example.

Though only the case of an element using SiC is described in each of theabove-mentioned embodiments, the present invention can be applied to anelement using other semiconductor materials such as silicon, galliumarsenide, or the like. In particular, it can be effectively applied toan element using a wide gap semiconductor material, such as diamond orgallium nitride.

In the above-mentioned first to sixth embodiments, though thedescription is made as to the case of an element of which the driftlayer 2 of a low impurity density is the n-type, the structure of thepresent invention is applicable in the case of an element of which thedrift layer is the p-type, by replacing n-type regions of othercomponents with p-type regions and by replacing the p-type regions withn-type regions.

INDUSTRIAL APPLICABILITY

As is apparent from the description of each embodiment as mentionedabove, in a field effect semiconductor device according to the presentinvention, a field effect transistor having a high withstand voltage inthe normally off state and having a low ON-state resistance even in thecase of a low gate voltage at the ON-state is realizable by providingwith a second conductive type buried gate region, a second conductivetype buried gate contact region, a second conductive type gate contactregion and a MOS gate. Since the gate voltage may be low, thereliability of the gate insulating film is improved.

In the case that the gate is divided into a buried gate and a MOS gate,each gate can be controlled independently and the ON-state resistancecan be further reduced.

By forming the second conductive type buried gate contact region ofimpurities of which the activation ratio is higher than that of thesecond conductive type buried gate region, the conductivity modulationis carried out effectively, and the ON-state resistance can be furtherreduced.

What is claimed is:
 1. A field effect semiconductor device comprising: adrift region of a first conductive type of a low impurity density formedon a drain region of the first conductive type of a high impuritydensity, a drain electrode formed on the face of said drain regionopposite to a face contacting to said drift region, a buried gate regionof a second conductive type formed in a central region adjacent to theopposite face to a face contacting to said drain region, in said driftregion; a buried gate contact region of a second conductive type formedin an end part region adjacent to said opposite face of a facecontacting to said drain region, in said drift region; a gate contactregion of a second conductive type formed on a part of said buried gatecontact region; a channel region of a first conductive type formed in aregion surrounded by said opposite face of said drift region and saidgate contact region; a source region of a first conductive type formedin a central region adjacent to the surface of said channel region; aninsulating film formed on a part of the surface of said gate contactregion, on the surface of said channel region and on a part of thesurface of said source region; a gate electrode provided on the surfaceof said insulating film and the surface of the gate contact region; anda source electrode provided on said source region.
 2. A field effectsemiconductor device in accordance with claim 1 characterized in that agate contact region of the second conductive type for connecting saidburied gate region and said buried gate contact region is formed in saiddrift layer of the first conductive type.
 3. A field effectsemiconductor device in accordance with claim 1 comprising a sourceelectrode formed on the entire surface of said gate electrode via aninsulating film and connected to said source region.
 4. A field effectsemiconductor device in accordance with claim 1 comprising a first gateelectrode formed so as to contact said gate contact region and a secondgate electrode which formed so as to oppose said channel region via saidinsulating film.
 5. A field effect semiconductor device comprising: adrift region of a first conductive type of a low impurity density formedon a region of a high impurity density; a channel region of a firstconductive type formed in a range broader than a buried gate region onsaid buried gate region; a source region of a first conductive typeformed in a central region adjacent to the surface of said channelregion; an insulating film formed on the surface of said drift region,on the side surfaces and on the surface of said channel region and onthe surface of said source region; a buried gate contact region of asecond conductive type formed in an end region adjacent to said oppositeface to the face contacting with said region of the high impuritydensity in said drift region; a gate electrode formed on said insulatingfilm and said buried gate contact region; and a source electrode formedon said source region.
 6. A field effect semiconductor devicecomprising: a drift region of a first conductive type of a low impuritydensity formed on an anode region of a second conductive type of a highimpurity density; an anode electrode formed on the face of said anoderegion opposite to the face contacting with said drift region; a buriedgate region of a second conductive type formed in a central regionadjacent to the opposite face to the face contacting with said anoderegion in said drift region; a buried gate contact region of a secondconductive type formed in an end region adjacent to said opposite faceof the face contacting with said drain region in said drift region; agate contact region of a second conductive type formed on a part of saidburied gate contact region; a channel region of a first conductive typeformed in a region surrounded by said opposite face of said drift regionand said gate contact region; a cathode region of a first conductivetype formed in a central region adjacent to the surface of said channelregion; an insulating film formed on a part of the surface of said gatecontact region, the surface of said channel region and the surface ofsaid cathode region; a gate electrode provided on the surface of saidinsulating film and the surface of said gate contact region; and acathode electrode provided on said cathode region.
 7. A field effectsemiconductor device in accordance with claim 6 characterized in that ahigh density region of the first conductive type is formed between saidanode region of the second conductive type and the drift region of thefirst conductive type.
 8. A field effect semiconductor devicecomprising: a drift region of a second conductive type of a low impuritydensity formed on a cathode region of a first conductive type of a highimpurity density; a cathode electrode formed on the face of said cathoderegion opposite to the face contacting with said drift region; a buriedgate region of a first conductive type formed in a central regionadjacent to the opposite face to the face contacting with said cathoderegion in said drift region; a buried gate contact region of a firstconductive type formed in an end region adjacent to said opposite faceto the face contacting with said cathode region in said drift region; agate contact region of a first conductive type formed on a part ofsaid-buried gate contact region; a channel region of a second conductivetype formed in a region surrounded by said opposite face of said driftregion and said gate contact region; an anode region of a secondconductive type formed in a central region adjacent to the surface ofsaid channel region; an insulating film formed on a part of the surfaceof said gate contact region, the surface of said channel region and thesurface of said anode region; a gate electrode provided on the surfaceof said insulating film and the surface of said gate contact region; andan anode electrode provided on said anode region.
 9. A fabricationmethod of a field effect semiconductor device comprising: the step offorming a drift region of a first conductive type of a low impuritydensity on a silicon carbide substrate of the first conductive type of ahigh impurity density; the step of forming a drain electrode on the faceof said drain region opposite to the face contacting with said driftregion; the step of forming a buried gate region of a second conductivetype in a central region adjacent to the opposite face to the facecontacting with said drain region within said drift region; the step offorming-a buried gate contact region of a second conductive type in anend region adjacent to said opposite face to the face contacting withsaid drain region within said drift region; the step of forming a gatecontact region of a second conductive type on a part of said buried gatecontact region; the step of forming a channel region of a firstconductive type in a region surrounded by said opposite face of saiddrift region and said gate contact region; the step of forming a sourceregion of a first conductive type in a central region adjacent to thesurface of said channel region; the step of forming an insulating filmon a-part of the surface of said gate contact region, the surface ofsaid channel region and the surface of said source region; the step offorming a, gate electrode on the surface of said insulating film and thesurface of the gate contact region; and the step of forming a sourceelectrode on said source region.
 10. A fabrication method of a fieldeffect semiconductor device comprising: the step of forming a driftregion of a first conductive type of a low impurity density on a siliconcarbide substrate serving as an anode region of a second conductive typeof a high impurity density; the step of forming an anode electrode onthe face of said anode region opposite to the face contacting with saiddrift region; the step of forming a buried gate region of a secondconductive type in a central region adjacent to the opposite face to theface contacting with said anode region within said drift region; thestep of forming a buried gate contact region of a second conductive typein an end region adjacent to said opposite face to the face contactingwith said drain, region within said drift region; the step of forming agate contact region of a second conductive type on a part of said buriedgate contact region; the step of forming a channel region of a firstconductive type in a region surrounded by said opposite face of saiddrift region and said gate contact region; the step of forming a cathoderegion of a first conductive type in a central region adjacent to thesurface of said channel region; the step of forming an insulating filmon a part of the surface of said gate contact region, the surface ofsaid channel region and the surface of said cathode region; the step offorming a gate electrode on the surface of said insulating film and thesurface of said gate contact region; and the step of forming a cathodeelectrode on said cathode region.
 11. A fabrication method of a fieldeffect semiconductor device in accordance with claim 10, furthercomprising the step of making the thickness of said anode region of thesecond conductive type thinner than the thickness of said drift region.12. A fabrication method of a field effect semiconductor device inaccordance with claim 10, further comprising: the step of removing saidanode region; and the step of forming the region of the secondconductive type by ion implantation in the drift region in which saidanode region is removed.
 13. A fabrication method of a field effectsemiconductor device comprising: the step of forming a drift region of asecond conductive type of a low impurity density on a silicon carbidesubstrate of a first conductive type of a high impurity density; thestep of forming a cathode electrode on the surface of said cathoderegion opposite to the face contacting with said drift region; the stepof forming a buried gate region of a first conductive type in a centralregion adjacent to the opposite face to the face contacting with saidcathode region within said drift region; the step of forming a buriedgate contact region of a first conductive type in an end region adjacentto said opposite face to the face contacting with said cathode regionwithin said drift region; the step of forming a gate contact region of afirst conductive type on a part of said buried gate contact region; thestep of forming a channel region of a second conductive type in a regionsurrounded by said opposite face of said drift region and said gatecontact region; the step of forming an anode region of a secondconductive type in a central region adjacent to the surface of saidchannel region; the step of forming an insulating film on a part of thesurface of said gate contact region, the surface of said channel regionand the surface of said anode region; the step of forming a gateelectrode on the surface of said insulating film and the surface of saidgate contact region; and the step of forming an anode electrode on saidanode region.